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1/18 rev. b ???e structure silicon monolithic integrated circuit u? `cd,`dvd ??`? product series power driver for car cds, dvds ?ekv type ?ekv ? ? package outlines figure1 Xp ? power dissipation figure2 ?? ? block diagram figure3 ? ? application figure4 y ? test circuit figure5 C ?(2ch)/(3ch)/?ste pping ?????(2ch)d ???/ ? on/off mute ?3.3v ?`i1ch ???` ?????? htqfp64v ?`????i ??joi function ?single chip ic with drivers fo r act(2ch)/loading(3ch)/sled(2ch )(for stepping motor). ?separated mute control for turned on/off at act/sled ?built in 3.3v regulator (1ch) ?adopti ng the package: htqfp64v equipped with a radiating metal on the mount side ?built in thermal-shut-down circuit. ?built in protection circuit for gnd fault
2/18 rev. b `???loading block ?ldctl ???RO the ldctl terminal is used to specify the output voltage. ?f,r 2 ??`?` 2-line control interface of f and r. ??sled block ?2 ?????` this sled terminal is for 2-phase stepping motors ?? supporting linear input ?pwm l??????? efficient drive by curr ent feedback pwm drive X` ?? linier btl drive systems ~?? absolute maximum ratings parameter symbol limits unit power mos ??R power mos power supply voltage slrnf pre /pow ??R pre-block and pow-block power supply voltage vcc,avm,ldvm S ?p ? power dissipation pd 1.9* ? operating temperature range topr -4085 ? storage temperature range tstg -55150 `??7070[mm], 1.6[mm] rohm standard board (size: 70 ? 70 [mm], thickness: 1.6 [mm]) ?X recommended operating conditions (??Rv??S?p???]O?) (set the power supply voltage ta king allowable dissipation into considering) parameter symbol min typ max unit power mos ??R power mos power supply voltage slrnf 4.5 8 10 pre /pow ??R pre-block and pow-block power supply voltage vcc,avm,ldvm 4.5 8 10 *vccRldvm
3/18 rev. b ?? 1 electrical characteristics (???? ta=25, vcc=powvccld,sl=8v ,avm=regvcc=5v, vc=1.6 5v,slrnf=3.3) (unless otherwise noted ta=25, vcc=powvccld,sl=8v ,avm=regv cc=5v, vc=1.65v,slrnf=3.3) parameter symbol min. typ. max. unit condition circuit current or quiescent current iq1 26.5 38.4 ma vcc=regvcc=powvcc=8[v] mute r mute circuit current ist1 19.5 28.3 ma vcc=regvcc=powvcc=8[v] ?`? sled driver block ??? input dead zone (one side) vdzsl 5 30 55 mv input output gain gmsl 0.082 0.27 0.106 0.130 0.43 a/v (v/v) slrnf=3.3 ??? output on resistor (upper) ronusl 2.4 3.6 il=500ma ??? output on resistor (lower) ronlsl 0.7 1.1 il=-500ma ?? output limit current ilimsl 0.105 0.35 0.136 0.167 0.55 a (v) slrnf=3.3 ? pwm frequency fosc 100 khz X`? actuator driver block ???R output offset voltage vofft -50 0 50 mv ??R output saturation voltage h vohft 0.45 0.8 v il=500ma ??R output saturation voltage l volft 0.45 0.8 v il=-500ma ?R voltage gain gvft 10.0 11.5 13.0 db bias terminal input current ibias - 75 120 a vbias=2.5v ?? operational amplifier block ???R input offset voltage vopof -5 0 +5 mv input bias current iopib 300 na ??R common mode input range vopicm 0.3 vcc-1.2 ` max output source current isource 500 800 a max output sink current isink 2 m `` slew rate sr 0.8 v/s `???? loading driver block input terminal input current iinl 87 130 a ldin=5v ldctl ldctl terminal output current ildcl 0.5 ma ldctl=5v ???R output offset voltage vofld -50 0 50 mv ??R output saturation voltage h vohld 1.1 1.4 v il=500ma ??R output saturation voltage l volld 0.45 0.8 v il=-500ma ?R voltage gain gvld 7.5 9.0 10.5 db ldctl=1v ?`` regulator reg ?R reg output voltage vreg 3.13 3.3 3.47 v il=200ma ?O????this product is not designed for protection aga inst radioactive rays.
4/18 rev. b ?? 2 electrical characteristics (???? ta=25, vcc=powvccld,sl=8v ,avm=regvcc=5v, vc=1.6 5v,slrnf=3.3) (unless otherwise noted ta=25, vcc=powvccld,sl=8v ,avm=regv cc=5v, vc=1.65v,slrnf=3.3) parameter symbol min. typ. max. unit condition mute1 high ??R 1 input high level voltage vih1 2.0 v low ??R 1 input low level voltage vil1 0.4 v high ? 1 input high level current iih1 180 270 ua vmute1=5v low ? 1 input low level current iil1 -10 0 10 ua vmute1=0v mute2 high ??R 2 input high level voltage vih2 2.0 v low ??R 2 input low level voltage vil2 0.5 v high ? 2 input high level current iih2 86 130 ua vmute2=5v low ? 2 input low level current iil2 -10 0 10 ua vmute2=0v ?O????this product is not designed for protection aga inst radioactive rays.
5/18 rev. b 1 ? fig.1 package outlines BD7966EKV lot.no
6/18 rev. b Xp fig.2 power dissipation 0 0.5 1 1.5 2 2.5 3 0 25 50 75 100 125 150 power dissipation : pd(w) rohm standard board (size: 70 70 [mm]), thickness: 1.6 [mm]) ja = 65.8 / w 85 `??g? c 70701.6mmt 65.8/w ?? ta ambient temperature : ta() S?p?pdw
7/18 rev. b ldctl3 ldctl2 ldctl1 ldo1r ldo1f ldo2r ldo2f ldo3r ldo3f ldi1r ldi1f ldi2r ldi2f ldi3r ldi3f mute2 mute1 ldvm2 opii2 slrnf2 slrnf2 test tmon opout1 powgnd1 vcc powgnd3 slin1- slin1o slin2o slin2- regvcc regout reggnd regvcc pregnd opii3 opout3 opii4 opout4 opin4 opii1 opout2 powgnd2 ldvm1 slrnf1 slrnf1 slo1- slo1+ slo2- slo2+ powgnd4 powgnd4 out1r out1f out2r out2f powgnd5 avm avm opin3 powgnd5 powgnd3 vc 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 63 64 level shift loding control level shift loding control level shift loding control mute1 mute2 pre logic ff limit osc pre logic ff limit level shift temp. monitor level shift 35 36 38 37 57 3 26 .3 ?? fig.3 block diagram
8/18 rev. b h pin desription no. symbol description no. symbol description 1 regvcc ?`` powpmos ? power supply for regulator powpmos 64 opout4 op 4 op output 4 2 regvcc ?`` powpmos ? power supply for regulator powpmos 63 opii4 op ? 4 op inverting input terminal4 3 regout ?`` regulator output 62 opin4 op ?? 4 op non-inverting input terminal4 4 reggnd ?`` gnd gnd for regulator 61 opout3 op 3 op output3 5 powgnd1 `????`gnd1 power gnd1for loading block 60 opii3 op ? 3 op inverting input terminal 3 6 ldo3f `??? c3 ?`? loading block ch3 forward output terminal 59 opin3 op ?? 3 op non-inverting input terminal3 7 ldo3r `??? c3 ` loading block ch3 reverse output terminal 58 vc bias input terminal 8 ldvm1 `????`? 1 power supply 1 for loading block 57 pregnd pre gnd gnd for pre-block 9 ldo2f `??? ch2 ?`? loading block ch2 forward output terminal 56 slin1o slin1 ? op slin1 pre-op output 10 ldo2r `??? ch2 ` loading block ch2 reverse output terminal 55 slin1- slin1 ? op ? slin1 pre-op inverting input terminal 11 powgnd2 `????`gnd2 loading block power gnd2 54 slin2o slin2 ? op slin2 pre-op output 12 ldo1f `??? ch1 ?`? loading block ch1 forward output terminal 53 slin2- slin2 ? op ? slin2 pre-op inverting input terminal 13 ldo1r `??? ch1 ` loading block ch1 reverse output terminal 52 opout1 btl ch1 ? op btl block ch1 pre-op output 14 ldctl1 `????RO ch1 loading block output voltage setting terminal ch1 51 opii1 btl ch1 ? op ? btl block ch1 pre-op inverting input terminal 15 ldctl2 `????RO ch2 loading block output voltage setting terminal ch2 50 opout2 btl ch2 ? op btl block ch2 pre-op output 16 ldctl3 `????RO ch3 loading block output voltage setting terminal ch3 49 opii2 btl ch2 ? op ? btl block ch2 pre-op inverting input terminal 17 ldvm2 `????`? 2 power supply 2 for loading block 48 powgnd5 X`?`gnd5 power gnd5 for actuator block 18 ldi1r `??? ch1 ` loading block ch1 reverse input terminal 47 powgnd5 X`?`gnd5 power gnd5 for actuator block 19 ldi1f `??? ch1 ?` loading block ch1 forward input terminal 46 out2f btl ch2 ?? btl block ch2 non-inverted output terminal 20 ldi2r `??? ch2 ` loading block ch2 reverse input terminal 45 out2r btl ch2 ? btl block ch2 inverted output terminal 21 ldi2f `??? ch2 ?` loading block ch2 forward input terminal 44 out1f btl ch1 ?? btl block ch1 non-inverted output terminal 22 ldi3r `??? c3 ` loading block ch3 reverse input terminal 43 out1r btl ch1 ? btl block ch1 inverting output terminal 23 ldi3f `??? c3 ?` loading block ch3 forward input terminal 42 avm X`?`? power supply for actuator block 24 mute2 mute 2 terminal mute2 41 avm X`?`? power supply for actuator block 25 mute1 mute 1 terminal mute1 40 powgnd4 X`?`gnd4 power gnd4 for actuator block 26 vcc pre ? power supply for pre-block 39 powgnd4 X`?`gnd4 power gnd4 for actuator block 27 tmon ???` temperature monitor 38 slo2+ ?? ch2 sled block ch2 non-inverted output terminal 28 test test 37 slo2- ?? ch2 ? sled block ch2 inverted output terminal 29 slrnf2 ??? 2 sled block current detection terminal 2 36 slo1+ ?? ch1 sled block ch1 non-inverted output terminal 30 slrnf2 ??? 2 sled block current detection terminal 2 35 slo1- ?? ch1 ? sled block ch1 inverted output terminal 31 slrnf1 ??? 1 sled block current detection terminal 1 34 powgnd3 ???`gnd3 power gnd3 for sending block 32 slrnf1 ??? 1 sled block current detection terminal 1 33 powgnd3 ???`gnd3 power gnd3 for sending block
9/18 rev. b ldctl3 ldctl2 ldctl1 ldo1r ldo1f ldo2r ldo2f ldo3r ldo3f ldi1r ldi1f ldi2r ldi2f ldi3r ldi3f mute2 mute1 ldvm2 opii2 slrnf2 slrnf2 test tmon opout1 powgnd1 vcc powgnd3 slin1- slin1o slin2o slin2- regvcc regout reggnd regvcc pregnd opii3 opout3 opii4 opout4 opin4 opii1 opout2 powgnd2 ldvm1 slrnf1 slrnf1 slo1- slo1+ slo2- slo2+ powgnd4 powgnd4 out1r out1f out2r out2f powgnd5 avm avm opin3 powgnd5 powgnd3 vc 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 63 64 level shift loding control level shift loding control level shift loding control mute1 mute2 pre logic ff limit osc pre logic ff limit level shift temp. monitor level shift 35 36 38 37 57 3 26 vcc(pre)=8v vc=1.65v m regvcc=5v m powvcc(act)=5v m m .4 ? fig.4 application circuit
10/18 rev. b
11/18 rev. b y?? test circuit (all) ldctl3 ldctl2 ldctl1 ldo1r ldo1f ldo2r ldo2f ldo3r ldo3f ldi1r ldi1f ldi2r ldi2f ldi3r ldi3f mute2 mute1 ldvm2 opii2 slrnf2 slrnf2 test tmon opout1 powgnd1 vcc powgnd3 slin1- slin1o slin2o slin2- regvcc regout reggnd regvcc pregnd opii3 opout3 opii4 opout4 opin4 opii1 opout2 powgnd2 ldvm1 slrnf1 slrnf1 slo1- slo1+ slo2- slo2+ powgnd4 powgnd4 out1r out1f out2r out2f powgnd5 avm avm opin3 powgnd5 powgnd3 vcc1 am 26 fwd 3 am 23 rev 3 am 22 fwd 2 am 21 rev 2 am 20 fwd 1 am 19 rev 1 am 18 am 17 mute 1 a m2 5 mute 2 a m2 4 loading unit loading unit loading unit ld ctl3 ld ctl2 am 14 am 15 am 16 ld ctl1 am 8 am reg il a b vm3 sw8 vcc2 op amp unit op amp unit op amp unit op amp unit op amp unit op amp unit vc am avm btl unit btl unit sl unit sl unit slrnf unit slrnf unit pin check pin check act op sl op vc 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 63 64 level shift loding control level shift loding control level shift loding control mute1 mute2 pre logic ff limit osc pre logic ff limit level shift temp. monitor level shift 3 26 35 37 36 38 56 .5-1 y fig.5-1 test circuit
12/18 rev. b y? test circuit (unit) vp (27,28) pin check c a b a ipin vpin ip sw p.c. op amp unit 61,64 59,62 a b c b a a b c vbop vof(3,4) vnfr(1,2,3,4) 10k vin 1m 10k opout vm (61,64) (50,52) 60,63 sw1 0.2v il+ b a vc am (61,64) (50,52) am (59,62) sw2 sw3 sw4 a a 49,51 50,52 slop&actop?ic?vc??A? slop&actop+ terminal is connected with vc in ic. vcc1 a b c rslrnf slrnf vslrnf slrnf unit sw7 a amrnf (ch1,ch2) a b a b vm (43,45) (7,10,13) ilr ilf sw6 vm (44,46) (6,9,12) vo(1,2) or vold(1,2,3) c 0.2v c 0.2v am(7,10,13) (43,45) am(6,9,12) (44,46) +- rl rl=8 d d a a loading unit btl unit sl unit =3.3 sw5 vm (35,37) vm (36,38) vosl(1,2) am (35,37) am (36,38) a b c d a b c d 0.2v il+ il- + - rl a 0.2v a 47uh rl=8 .5-2 y fig.5-2 test circuit
13/18 rev. b y?? table of measure circuit switches position ???? ta=25, vcc1vcc,ldvm =8v,vcc2(regvcc,avm)=5v vc=1.6 5v vbop=2.5v rl=8????a unless otherwise noted ta=25 , vcc1vcc,ldvm=8v,vcc2(regvcc,avm)=5v vc=1.65v vbop=2.5v rl= 8the switch not specified a ? designation ? symbol switch condition or quiescent current iq1 a a a a a a a a mute r circuit current at mute ist1 mute=gnd ?`? sled driver block ??? input dead zone (one side) vdzsl a b b a a a b a input output gain gmsl c ??? output on resistor (upper) ronusl d b ic=500ma ??? output on resistor (lower) ronlsl ic=500ma ?? output limit current ilimsl a c ? pwm frequency fosc b a mute=1.9v,vin=1.45v X`? actua tor driver block ???R output offset voltage vofft a a a a a b a a (vm50,vm52)-vc ??R output saturation voltage h vohft b b d vin=0v,il=0.5a ??R output saturation voltage l volft vin=0v,il=0.5a ?R voltage gain gvft b bias terminal input current ibias a c a ?? operational amplifier block ???R input offset voltage vopof a a a a a a a a (vm61,vm64)-vc,mute=1.9v input bias current iopib b c mute =1.9v,vc=1.65v,vbop=1.65v ??R common mode input range vopicm a vbop ??`?vof y vbop sweep, vof measurement ` max output source current isource a c max output sink current isink `???? loading driver block input terminal input current iinl a aaaaa aaldctl=5.0v ldctl terminal ldctl output current ildc1 mute=rev=for=0.6v ???R output offset voltage vofld b mute=0.6v,rev=1.9v for=0.5v or for=1.9v rev=0.5v ??R output saturation voltage h vohld d il=500ma ??R output saturation voltage l volld il=500ma ?R voltage gain gvld b mute=0.6v,for=1.9v,rev=0.6v, ldctl=2.0v ?`` regulator reg ?R reg output voltage vreg a a a a a a a b il=200ma
14/18 rev. b Ch functional description 1. mute1,2 (pin 25,24) ????2v ?????0.5v ????????? mute1 act on/off ? mute2 ?? on/off ? mute1,2 ?`?????? each driver's on/off can be switched by inputting combinations of h-level signal (higher than 2v) and l-level signal (lower th an 0.5v) to this terminal. mute1 controls on/off in the act block. mute2 controls on/off in the sled block. neither mute1, 2 control the loading block. `???the content of the mode switch is as follows. mute1,2 ? each driver l mute_on h mute_offactive 2. `??? loading block ????2?????0.5v ???`?????? f/r ??? ?? loading driver's f/r (normal rotation and reverse) can be switc hed by inputting h level (higher than 2v) or l levels (lower th an 0.5v) to the input terminal. `???the content of the mode switch is as follows. ldi*f ldi*r ldo*f ldo*r mode l l hiz hiz `? open l h l h ?` forward h l h l ` reverse h h 1/2ldvm 1/2ldvm ?` brake ?R 1/2ldvm ??the output voltage is 1/2ldvm standard. for????rg??ms ??????????? ?ms ?????? the ld f/r input of this ic need the signal time more than 10ms. especially, note the chattering of the input signal. please do not input pwm signal of the cycle that is faster than that of 10ms
15/18 rev. b 3. ?? sled block 1????slin??slrnf torque command slin/ output current detection terminals slrnf ??? slin ? slrnf????? the relation between the torque command input ( slin) and the output current detection terminals input ( slrnf) is as follow: _sl ???sl sl???Q?? the input-output gain ( gmsl ) and the output-limit current ( ilimsl ) depend on the resistance of slrnf (output current detection resistor). ???? refer to the formula in the following table. 2)?? gain formula (typ.) sled input-output gain 0.35 /slrnf (a/v) ?? output-limit current 0.45 / slrnf (a) 3) k? pwm oscillation frequency the pwm oscillation for driving the spindle is internal oscilat ing system. ??k??k????k? 100khztyp.? the oscillating frequency is 100 khz (typ.). 3. `???? thermal-shutdown ?`??????oi?????`S?p????? ??S?p????B?????????N175typ.?`?????? ?????? ???27pin???`??high ?`????low ?`????? a thermal shutdown circuit (over-temperature protection circuit) is built in to prevent the ic from thermal breakdown. use the ic under the power dissipation. if the ic is left running over the power dis sipation, the package temperature rises, and the thermal-shutdo wn circuit works at the junction temperature of 175 (typ.) (the outputs of all the channels are turned off). this operation can be detected with tmon(27pin). a thermal shut down is operating if the high output. a thermal shutdown is no- operating if the low output. tmon tmon output ?B state l t.s.d (? mute off) t.s.d is no-operating.(al l circuits mute off) h t.s.d ? mute on t.s.d is operating.a ll circuits mute on vc slrnf slin ? (dead zone-) ? (dead zone+)
16/18 rev. b 4. N?` muting functions 1) vcc ?` vcc-drop muting vccpin26?R 3.9vtyp.????????`???????R 4.1v ?????? when the voltage at vcc terminal (pin 26) drops to a value lowe r than 3.9v (typ.), the outputs of all the channels are turned high-impedance. when the voltages rise to more then 4.1v (typ.), the ic starts operating again. 2) vc ?` vc-drop muting vc ?pin58?R 0.7vtyp.???btl ????`?????vc R 1.0v O when the voltage at vc terminal (pin 58) drop to lower than 0.7 v (typ.) , the outputs of btl block and sending block are turned high-impedance. set the vc terminal voltage to larger th an 1.0v. 5. ?jo protection ci rcuit for gnd fault ????g`??j??p??joi?? ???`????????j????? ?p?X``???? protection circuit for gnd fault is contained to prevent from b reaking caused by short between output pin and gnd. make sure output pin should not short to gnd. however in case gnd fault occurs, internal circuit prevents ic from breaking by limiting current. (only the actuator block and the loading block)
17/18 rev. b ??? cautions on use ?? by pass capacitor o?g?????????0.1f?A??`????? ` ????????10f?? connect bypass capacitor (0.1 ? f) close to the ic pin between power supplies. also, adopting c apacitor which is greater capacity and small esr close to power supply terminal for reducing impedance. j?jg` supply fault, ground fault, and short-circuit between output terminals. ??? g`?j???g`??j??g`???`??? ???H?????????p?????k??? short-circuits between output pin-vcc, output pin-gnd, or outpu t terminals (load short) must be avoided. make sure that the ics are installed on the board in proper dir ections. mounting the ics in improper directions may damage th em or produce smoke. test test terminal test ? ic ????????`?? gnd ?`??? the test terminal is pulled down in ic, therefore use it as ope n or shorted with gnd. . ?`gnd g??A?????k?????????? the capacitor connected between g nd and regulator output avoide d oscillating, so use the good o ne of the temperature character istic. ???ic ??R???????? basically, please avoid impressing the voltage below the sub po tential of ic to the terminal. ???????ic ?R(gnd)??`??]?? examine it after considering the operation margin when the output of each driver falls as follows sub voltage (gnd) of ic by t he counter electromotive force of the load. ~???? about absolute maximum ratings ??R?????~?????????`?`?? `?`??????~?????`????`????? ??? exceeding the absolute maximum ratings, such as the applied vol tage or the operating temperature range, may cause permanent de vice damage. as these cases cannot be limited to the broken short mode or th e open mode, if a special mode where the absolute maximum ratin gs may be exceeded is assumed, it is recommended to take mechanica l safety measures such as attaching fuses. ??? about power supply lines `????U??-gnd g?????????? ??????????????T??}?????_JQ? as a measure against the back current regenerated by a counter electromotive force of the motor, a capacitor to be used as a r egenerated-current path can be installed between t he power supply an d gnd and its capacitance value should be determined after careful check that any problems, for example, a leak capacitance of the electrolytic capacitor a t low temperature, are not found in various characteristics. gnd ?? about gnd potential gnd ????B???????? the electric potential of the gnd terminal must be kept lowest in the circuitry at any operation states. O??? about thermal design gH??B?S?p?pd?????`??O??? with consideration of the power dissipation (pd) under conditio ns of actual use, a thermal design provided with an enough marg in should be done. ????? about operatio ns in a strong electric field ?????`??????? when used in a strong electric field, note that a malfunction m ay occur. aso ic ??H?? tr ~???? aso ????O? when using this ic, the output tr must be set not to exceed the values specified in the absolute maximum ratings and aso.
18/18 rev. b ?? thermal shutdown circuit (thermal shutdown: tsd) ic ???tsd i???????????`???`??B?? ??????? ic ???????ic o?^?????? ????BA????????? this ic built in a thermal shut down circuit (tsd circuit). when the chip temperature reaches the value shown below, the co il output to the motor will be set to open. the thermal shutdown circuit is designed only to shut off the i c from a thermal runaway and not intended to protect or guarant ee the entire ic functions. therefore, users cannot assume that the tsd circuit once activa ted can be used continuously in the subsequent operations. `?`?? about earth wiring patterns ? gnd ? gnd ? gnd ?`? gnd ?`?x?`???? ?R? gnd ?R????????`???X? ?? gnd ?`?????? when a small signal gnd and a large current gnd are provided, i t is recommended that the large current gnd pattern and the sma ll signal gnd pattern should be separated and grounded at a single point of the refer ence point of the set in order to prevent the voltage of the sm all signal gnd from being affected by a voltage change caused by the resistance of the pa ttern wiring and the large current. make sure that the gnd wiring patterns of the external componen ts will not change, too. ??? about each input terminal ic ?? ic ??g?x p + ` p P?? p ??? n ?? pn ????N???ic ??vS??????? ??????h??`???????????? gndp P??R??????????????? ?ic ??R????r??R???????R?????? ??R?R????^??? this ic is a monolithic ic which has a p + isolations and p substrate to isolate elements each other. thi s p layer and an n layer in each element form a pn junction to construct various parasitic elements. du e to the ic structure, the parasitic elements are inevitably cr eated by the potential relationship. activation of the p arasitic elements can cause in terference between circuits and may result in a malfunction or, consequently, a fatal damage. therefore, make sure that the ic must not be used und er conditions that may activate the parasitic elements, for exa mple, applying the lower voltage than the ground level (gnd, p substrate) to the input terminals. in addition, do not apply the volt age to input terminals withou t applying the power supply voltage to the ic. also while appl ying the power supply voltage, the voltage of each input terminal must not be over th e power supply voltage, or within the guaranteed values in the electric characteristics. tsd on ?[]typ. tsd on temperature [ ? c] (typ.) ????[]typ. hysteresis temperature [ ? c] (typ.) 175 25
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